A half-bridge is a power converter comprising two power switches, e.g. transistors, one referred to as the low side transistor, and the other referred to as the high side transistor. Each transistor is driven by separate drive circuits, i.e. a low side driver and a high side driver.
In the art well known controlling systems for a high side driver comprise a pulse technique, where narrow set and reset current pulses are transmitted to the high side driver, in which a latch is placed to restore the original control signal. Such a system is known from U.S. Pat. No. 5,514,981 “Reset dominant level-shift circuit for noise immunity” and U.S. Pat. No. 5,105,099 “Level shift circuit with common mode rejection”.
In pulse control a major problem is common mode dv/dt induced currents in the current paths of the set and reset nodes, arising from parasitic capacities in current pulse generators. The dv/dt at the output terminal (offset voltage) of the output stage can reach very high levels—thus even very small parasitic capacitances will result in dv/dt common mode induced currents. The common mode noise can cause false operation of the output switch, resulting in shoot-through in the power stage.
Conventionally, the current pulses have been converted into voltage pulses in the high side driver by means of two pull up resistors. This approach does not in it self provide any common mode rejection and additionally circuits have been mandatory.
One way of solving problems due to common mode noise has been to add low pass filtering combined with adjustment of thresholds of the set/reset levels in order to obtain a reset dominant function, leading to a more predictable operation. Unfortunately this approach compromises speed and power efficiency because of the low pass filtering, which calls for an increase of the width of the current pulses.
Another approach has been to add logic circuitry after said pull up resistors to suppress common mode signals; this however involves a substantial amount of gate circuitry.
Lowering of the power consumption in the driver to achieve high efficiency in the system can be obtained by lowering the gate drive voltage, preferably to logic level (5 Volt). By doing so the speed performance of the system is also increased. Reducing the gate drive voltage also reduces the noise margin for the voltage drop over the pull up resistors. Therefore level shift circuits based on pull up resistors are challenged when the load terminal is negative with respect to ground. This is caused by the fact that the voltage drops over the pull up resistors are limited which can course false operation of the MOSFET's. The situation of negative load terminal voltage occurs in situations of ringing and when the body-diode in the low side MOSFET of the half bridge is conducting.
In general, the use of pull up resistors is not suitable for logic level driver voltage because of the negative load terminal voltage that must be expected to compromise the logic level of the high side set/reset inputs.